Leveraging dynamic reconfiguration to increase fault-tolerance in FPGA-based satellite systems

Performance requirements for on-board processing of satellite instrument data are steadily increasing. This demonstrator shows how today’s SoCs for satellite payload processing can be extended with high-speed interfaces and computing power utilizing commercial dynamically reconfigurable FPGAs. Reconfigurable hardware further allows for changing or adapting payload processing during the flight mission, even if not foreseen at design time. Moreover, dynamic partial reconfiguration allows for implementing time-sharing of the reconfigurable resources between different applications, thus increasing the area and energy efficiency. The use of commercial SRAMbased FPGAs will experience single event effects (SEE) due to radiation in configuration memory, logic resources and block rams. Therefore, a unit for detection (readback scrubbing), and correction on the processing FPGAs has been developed to increase the reliability of the system. To prove the effectiveness of the system a scalable prototyping environment has been developed [1] combining dynamically reconfigurable Xilinx FPGAs, a rad-hard SoC (SpaceWire Remote Terminal Controller, based on a LEON2FT), and emerging avionic interfaces (e.g. , SpaceFibre) additionally to established ones (e.g. , SpaceWire, MIL or CAN). The modular RAPTOR FPGA prototyping platform has been used to create a highly scalable platform, where the amount of reconfigurable resources (e.g. , number of FPGAs or FPGA type) can be easily modified. The RAPTOR-based demonstrator is depicted in Fig.1. Further details on the architecture of the system are presented in [2].